Computer Architecture MCQs

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1. Which of the following components is responsible for temporarily storing data and instructions that the CPU needs to access quickly?
(A) Random Access Memory (RAM)
(B) Hard Disk Drive (HDD)
(C) Central Processing Unit (CPU)
(D) Solid State Drive (SSD)

2. What is the purpose of the Arithmetic Logic Unit (ALU) in a CPU?
(A) To manage the flow of data between the CPU and memory
(B) To store frequently accessed data for quick retrieval
(C) To perform mathematical and logical operations on data
(D) To control the overall operation of the computer system

3. Which of the following is NOT typically a function of the Control Unit (CU) in a CPU?
(A) Fetching instructions from memory
(B) Decoding instructions to determine what operation to perform
(C) Executing instructions in the correct sequence
(D) Performing arithmetic operations on data

4. What is the purpose of a cache memory in a computer system?
(A) To permanently store data and programs
(B) To provide additional storage space for the CPU
(C) To temporarily store frequently accessed data and instructions
(D) To manage the communication between different components

5. Which computer architecture feature allows a CPU to execute multiple instruction streams concurrently?
(A) MIMD
(B) SIMD
(C) SISD
(D) MISD

6. Which component permanently stores data even when power is off?
(A) Cache memory
(B) RAM
(C) Hard Disk Drive (HDD)
(D) Optical Disk Drive (ODD)

7. The bus in a computer system is used for:
(A) Communicating between different components
(B) Storing data temporarily
(C) Performing arithmetic operations
(D) Executing program instructions

8. Which is NOT a characteristic of RISC architecture?
(A) Register-based operations
(B) Few addressing modes
(C) Simple instructions
(D) Large number of instructions

9. What does “pipeline” mean in computer architecture?
(A) Long-term storage device
(B) A series of steps through which instructions pass
(C) Network protocol
(D) High-speed memory module

10. Which memory has the fastest access speed?
(A) HDD
(B) Cache memory
(C) SSD
(D) ODD

11. What is the primary function of the motherboard?
(A) Provide power
(B) House CPU and memory
(C) Store data permanently
(D) Connect and communicate between components

12. Which is NOT a characteristic of von Neumann architecture?
(A) Separate memory and CPU
(B) Parallel processing
(C) Same memory for data and instructions
(D) Stored-program concept

13. What role does BIOS play?
(A) Manages CPU-GPU interaction
(B) Manages file systems
(C) Allocates memory
(D) Initializes hardware at startup

14. Which is a volatile memory?
(A) HDD
(B) Flash
(C) ODD
(D) RAM

15. Which pipeline stage fetches instructions?
(A) Decode
(B) Execute
(C) Writeback
(D) Fetch

16. Advantage of parallel processing?
(A) Increased complexity
(B) Slower performance
(C) Reduced power consumption
(D) Higher cost

17. Which component stores firmware?
(A) CPU
(B) GPU
(C) BIOS/UEFI
(D) SSD

18. Purpose of Address Bus?
(A) Carry data
(B) Transmit control signals
(C) Carry memory addresses
(D) Manage interrupts

19. What does “bit-width” refer to?
(A) Memory address size
(B) Bits processed per instruction
(C) Bus width
(D) Parallel bits

20. Smallest and fastest memory?
(A) ODD
(B) RAM
(C) HDD
(D) Cache

21. Characteristic of Harvard architecture?
(A) Single memory
(B) Single bus
(C) Separate data and instruction memory
(D) Limited instruction set

22. Purpose of Floating Point Unit (FPU)?
(A) Integer arithmetic
(B) I/O control
(C) Memory management
(D) Floating-point arithmetic

23. Feature allowing multiple processors to work together?
(A) SIMD
(B) MIMD
(C) SISD
(D) MISD

24. Role of Northbridge chipset?
(A) CPU–RAM communication
(B) Power distribution
(C) I/O control
(D) Security

25. Non-volatile long-term storage memory?
(A) Cache
(B) SSD
(C) RAM
(D) Registers

26. NOT a superscalar feature?
(A) Multiple instruction execution
(B) Out-of-order execution
(C) Increased instruction set complexity
(D) Multiple execution units

27. Cache coherence protocol ensures:
(A) Data consistency
(B) Power control
(C) Clock sync
(D) Cache allocation

28. Advantage of RAID?
(A) Less redundancy
(B) Reduced capacity
(C) Higher data transfer rates
(D) Limited fault tolerance

29. What is a clock cycle?
(A) CPU instruction execution frequency
(B) Bus speed
(C) Memory size
(D) Number of cores

30. Technology predicting future memory access?
(A) Cache
(B) Virtual memory
(C) Interleaving
(D) Prefetching

31. Purpose of IRQ line?
(A) Data transfer
(B) Request CPU attention
(C) Control execution
(D) Clock sync

32. What is a bus?
(A) Storage device
(B) Speed unit
(C) Software
(D) Communication system

33. Firmware is stored in:
(A) RAM
(B) Flash
(C) Cache
(D) ROM

34. SSD advantage over HDD?
(A) Higher capacity
(B) Faster access
(C) Lower cost
(D) More durability

35. Role of Power Supply Unit (PSU)?
(A) Control clock speed
(B) Convert electrical power
(C) Store data
(D) Network management

36. Latency refers to:
(A) Write time
(B) CPU frequency
(C) Delay before response
(D) Clock speed

37. Purpose of a bus?
(A) Increase CPU power
(B) Provide storage
(C) Enable component communication
(D) Manage cooling

38. Example of volatile storage?
(A) Cache memory
(B) Flash drive
(C) HDD
(D) ROM

39. BIOS stands for:
(A) Basic Integrated OS
(B) Basic Input Output System
(C) Binary Input Output System
(D) Binary Integrated OS

40. Data lost when power is removed occurs in:
(A) ROM
(B) Flash
(C) DRAM
(D) HDD

41. Typical CISC feature?
(A) Few instructions
(B) Microcode execution
(C) Simple one-cycle instructions
(D) Many addressing modes

42. Role of MMU?
(A) Cache management
(B) Data transfer
(C) Clock control
(D) Virtual to physical address translation

43. Fastest cache level?
(A) L3
(B) L2
(C) L1
(D) Main memory

44. Virtual memory is:
(A) Physical HDD memory
(B) OS memory abstraction
(C) Boot memory
(D) Cache

45. Multi-core processor means:
(A) Multitasking CPU
(B) Separate execution units
(C) Multiple cores on one chip
(D) External processors

46. Instruction Register stores:
(A) Current instruction
(B) Next instruction address
(C) Data transfer info
(D) Execution state

47. Function of interrupt?
(A) Pause execution
(B) Clean memory
(C) Request urgent CPU attention
(D) Manage power

48. Benefit of pipelining?
(A) Higher throughput
(B) Sequential processing
(C) Slower execution
(D) Simpler design

49. Memory for fast access, volatile?
(A) ROM
(B) Flash
(C) HDD
(D) DRAM

50. Overclocking means:
(A) Increasing cache
(B) Running CPU beyond rated speed
(C) CPU upgrade
(D) Lowering power

51. Purpose of fetch-decode-execute cycle?
(A) Memory management
(B) Process instructions
(C) I/O handling
(D) Data flow control

52. DMA stands for:
(A) Data Management App
(B) Direct Memory Access
(C) Dynamic Memory Allocation
(D) Digital Media Adapter

53. Memory for frequent quick access?
(A) Virtual
(B) Secondary
(C) ROM
(D) Cache

54. Bus width refers to:
(A) Memory size
(B) CPU speed
(C) Instruction register size
(D) Bits transferred simultaneously

55. Cache hit means:
(A) Cache full
(B) Data from RAM
(C) Data found in cache
(D) Access delay

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